Semiconductor memory and method for operating the same
US7203115B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 2005 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data additional circuit adds plural types of expectation data to be read from a refresh block to data read from other blocks, respectively, to generate plural read data strings. An error correction circuit detects errors for each read data string, and sets the most reliable result of the error detection results to be true. The error correction circuit decodes data to be read from the refresh block based on a true error detection result. Moreover, the error correction circuit corrects the error of the read data string corresponding to the true error detection result. Consequently, without extending the read cycle time, a refresh operation can be hid, and errors can be corrected simultaneously. By correcting a data error read from a bad memory cell of data retention characteristics, a refresh request interval can be extended, and power consumption during a standby period can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.