All digital reference frequency locking
US7203227B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2002 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Jun 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/2801
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.