Methods and apparatus for signal modification in a fractional-N phase locked loop system
US7203262B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 13, 2003 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | May 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop includes a buffer that synchronizes the transmission of the new count value to the completion of the previous count to avoid errors caused by dithering. The buffer is connected to a count input of the counter and transmits the new count upon receipt of the carryout signal from the counter. Alternatively, the transmission of the new value of N from the buffer is delayed after receipt by the buffer of a carryout signal from the counter. In another embodiment, a delayed version of the carryout signal is used to trigger the buffer to transmit the new count value to the counter. In another feature, a buffer synchronizes phase data to a reference signal before inputting it to a digital modulator of the phase locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.