Power-saving control circuitry of electronic device and operating method thereof
US7203855B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | May 10, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-saving control circuitry of an electronic device is provided. The power-saving control circuitry comprises a power control circuit, an oscillator, a clock pulse generator, a reserve circuit and a multi-enable module. When the electronic device enters a power saving mode, the oscillator stops generating oscillatory timing signals and the clock pulse generator stops generating operational clock signals. Because digital timing signals are generated by either the oscillatory timing signals or the operational clock signals, digital timing signals also stop. Furthermore, power to the flash ROM of the electronic device could be cut off by the signals sent to the oscillator, the clock pulse generator or the multi-enable module from the power control circuit as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.