Error correction for memory
US7203889B2 · kind B2 · utility
28Cited by
2References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller includes a read data module to read the user data and parity information, determine whether there is error in the user data based on the parity information, read the error correction information if there is error as determined based on the parity information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.