Compiling memory dereferencing instructions from software to hardware in an electronic design
US7203912B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jul 21, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Apr 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Electronic system functionality can be initially implemented as software code (e.g., in programming languages such as C, C++ or Pascal) and selectively converted to a hardware representation such as in hardware description language (e.g., VHDL, Verilog, HandelC, BachC, SpecC and System Verilog). In one aspect, software code representations comprising memory dereferencing operations (e.g., related to pointers, arrays and structs) may also be converted to a hardware representation. The newly converted hardware representation may be given control of a main communications network (e.g., system bus) of the electronic system to control the execution of the memory dereferencing operations (e.g., related to pointers, arrays and structs). In one embodiment, bus control may be via a bus control interface adapted for a particular kind of communications network (e.g., a processor bus, a system bus, a hierarchical bus, a cross bar, a multiplexer bus, a switch network and a point to point network). In another embodiment, a software memory dereferencer for executing memory dereferencing operations may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.