Timing circuit cad
US7203914B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2002 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Jun 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprises the steps of first dividing an area to be serviced into regions each small enough for there to be negligible inter-region transmission-line delay at target operating frequency. The dividing perimeters of each said region are then divided into segments suitable for approximating lumped transmission-line LKR and relevant parameters determined so that time delays over each such segment are substantially equal to cycle time of desired frequency divided by twice the number of segments. The capacitance of each segment is determined to be substantially equal to the largest envisaged load capacitance (including or preferably differential load capacitance) plus loop-to-loop interconnect capacitance plus active device (say and usually transistor) capacitance of voltage-transition regenerative means and addition to unloaded segments of padding capacitance calculated substantially to match the lumped line capacitance, and pitch/width of differencial transmission-line conductors is calculated using Wheeler's formula constrained by metallization factor involved. Finally…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.