System, method and program product for positioning I/O pads on a chip
US7203916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Feb 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49171
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file, cross-reference table, an I/O limit table, and an optional information file, a group switching current for each proposed I/O pad group is automatically calculated and compared to predetermined maximum switching current(s). If an I/O pad group exhibits a switching current that exceeds its predetermined maximum, corrective action is taken. Such action can include, for example, relocation of an I/O pad from an overloaded I/O pad group to another I/O pad group, insertion of an additional power pad into the overloaded I/O pad group, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.