Method and system for designing an integrated circuit with reduced noise
US7203921B2 · kind B2 · utility
2Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Apr 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/0005
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Noise current flowing to the outside of an IC (1) with respect to the capacitance value and arrangement location of a bypass capacitor (4) is calculated on the basis of the impedance of current paths (P1, P2) passing via a bypass capacitor (4) at the outside of the IC (1) and the impedance of the inside of IC (1) when viewed from power supply terminals (2, 3) of the IC (1). The capacitance value and arrangement location of the bypass capacitor (4) are determined on the basis of the calculation result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.