Method of forming a recess channel trench pattern, and fabricating a recess channel transistor
US7205199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Feb 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.