Method and apparatus for a semiconductor device having low and high voltage transistors
US7205630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | May 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.