On-chip termination for a high-speed single-ended interface
US7205787B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Nov 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus that provide accurate on-chip termination impedances for high-speed data interface circuits. One embodiment of the present invention provides a series termination impedance for an output driver as well as shunt termination impedances for a receive circuit. These impedances are dynamically adjusted to match a ratio of an external precision resistor. Multiple coarse and fine-grain adjustments are automatically performed by the hardware. Adjustment may occur at power up or at programmable periodic intervals, and one or both of the impedances may be updated each time an interface begins to transmit or receive data. A specific embodiment utilizes a reference resistance that is made up of a parallel combination of resistors connected through MOS transistors. This resistance is adjusted by connecting or disconnecting the parallel resistors until it matches a ratio of an external resistor. The switch settings that provide a match are then used to adjust the termination impedances at the input and output pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.