Methods and system for reducing effects of digital loop dead zones
US7205804B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Mar 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems for reducing effects of digital loop dead zones add phase randomness to one or more asynchronous signals that are to be synchronized with a digital loop system clock. Phase randomness is added in one or more of a variety of ways including, without limitation, non-harmonic asynchronous signals and variable phase delay. The invention can be implemented in a variety of types of digital loops including, without limitation, phase locked loops (“PLLs”). For example, a PLL receives a system clock signal, a digital reference signal, and a feedback signal. The digital reference signal and/or the feedback signal is asynchronous with the system clock signal. A phase of the asynchronous signal(s) is randomized and then synchronized with the system clock signal, prior to phase difference detection. This reduces effects of digital loop dead zones that are otherwise introduced by synchronization. The phase difference between the reference signal and the feedback signal is used to control a numerically controlled oscillator (“NCO”), which outputs the feedback signal. The NCO controls the feedback signal to minimize the phase difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.