Zero-bias-power level shifting
US7205819B2 · kind B2 · utility
14Cited by
8References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Apr 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for voltage level translation with zero static current is disclosed for interfacing devices at one supply voltage with devices at another supply voltage. The translation is achieved by using a modified current mirror circuit such that the current mirror is effectively turned off when the output reaches a steady state condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.