Radio frequency CMOS amplifier with enhanced linearity and power efficiency
US7205846B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Dec 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In general, the disclosure is directed to techniques for enhancing power efficiency and linearity in an RF power amplifier. In accordance with the invention, a combination of different class power amplifiers is implemented in a parallel configuration to overcome the trade-off that exists between power efficiency and linearity. In particular, a class A amplifier and a class B amplifier are arranged in parallel to produce a combined amplifier output for an input signal. With bias voltages set to achieve a desired operating ratio between the class A and class B amplifier, the combined amplifier can provide a high power gain over a larger input range. In addition, the class B amplifier can provide increased power efficiency for larger inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.