On-chip transistor degradation monitoring
US7205854B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2003 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Apr 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31727
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments of the invention include on-chip characterization of transistor degradation. In one embodiment, includes one or more functional blocks to perform one or more functions and an integrated on-chip characterization circuit to perform on-chip characterization of transistor degradation. The integrated on-chip characterization circuit includes a selectively enabled ring oscillator to generate a reference oscillating signal, a free-running ring oscillator to generate a free-running oscillating signal, and a comparison circuit coupled to the selectively enabled ring oscillator and the free-running ring oscillator. From the reference oscillating signal and the free-running oscillating signal, the comparison circuit determine a measure of transistor degradation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.