Highly parallel switching systems utilizing error correction II
US7205881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Mar 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device from the second stage network exceeds the number of outputs from a device into the first stage network. The latency through the entire system may be a fixed constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.