Tamper detection and secure power failure recovery circuit
US7205883B2 · kind B2 · utility
19Cited by
13References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 7, 2002 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A security system including a token and a host system. The token includes volatile random access memory for storing security data for use during a step of secure authentication, an interface for providing communication with a host system when coupled thereto, and a processor. The processor performs the steps of authenticating a host system and the token, providing secure information to the host system upon authentication therewith, and re-authenticating the host system and the token in response to receipt of the secure information after a reset of the token has occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.