Circuit and method for generating word line control signals and semiconductor memory device having the same
US7206252B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Oct 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for generating word line control signals that have a stable boosting margin of the sub-word line driver: The circuit includes a first address buffer, a pre-decoder unit, a second address buffer, a main decoder and a circuit for generating a word-line boosting signal. The second address buffer delays a refresh count signal for a predetermined time and generates an enable signal having a predetermined pulse width in response to a row address setup signal and the delayed refresh count signal, and receives and latches a pre-decoded row address signals to output decoded row address signals in response to the enable signal. Accordingly, the circuit for generating word line control signals is capable of obtaining a stable self-boosting margin when the semiconductor memory device operates in a refresh mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.