Method and apparatus for delayed recursion decoder
US7206363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Dec 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0054
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed maximum likelihood sequence estimation method and device. The method includes identifying candidate paths through a state trellis based on a group of observed data, where each candidate path corresponds to a best path through a trellis beginning at one of a possible prior states (and corresponding prior data bit or bits), and then selecting one of the paths based on candidate sequence selection information, typically prior state decisions (e.g., data symbols in the form of one or more bits). The path selection, in turn, provides decoding of symbols and data bit information for use in selecting one of the candidate paths in a subsequent stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.