Programmable feedback delay phase-locked loop for high-speed input/output timing budget management and method of operation thereof
US7206369B2 · kind B2 · utility
5Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Oct 12, 2001 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Nov 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.