Interrupt priority control within a nested interrupt system
US7206884B2 · kind B2 · utility
3Cited by
14References
20Claims
0Family size
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Key dates
| Filing date | Feb 11, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Dec 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4818
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.