Multi-port memory controller having independent ECC encoders
US7206891B2 · kind B2 · utility
7Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Jan 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.