Micro-operation un-lamination
US7206921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2003 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Jul 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type operands into a laminated micro-operation, and may generate unlamination information for the laminated micro-operation. The second decoder may generate from the laminated micro-operation and the unlamination information two or more micro-operations, where operands of the two or more micro-operations each correspond to a half of one of the SSE operands of the macroinstruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.