Edge protection process for semiconductor device fabrication
US7208326B2 · kind B2 · utility
9Cited by
3References
20Claims
0Family size
Inventors
Key dates
| Filing date | Oct 18, 2004 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Jan 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective layer substantially prevents the etching of the circumferential edge region, such that the formation of black silicon is substantially minimized during the etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.