Method and device for producing layout patterns of a semiconductor device having an even wafer surface
US7208350B2 · kind B2 · utility
3Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2004 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Aug 26, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.