Method of manufacturing multiple-gate MOS transistor having an improved channel structure
US7208356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2004 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Feb 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0245
Abstract
Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.