Reducing variation in reference voltage when the load varies dynamically
US7209060B2 · kind B2 · utility
7Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate load on the path is approximately constant. In case of the stages of an ADC, the sub-code generated by each stage during a sampling phase is used to estimate the load that would be offered, and the dummy load is added in the hold phase to keep the reference voltage constant in the hold phase, as desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.