Low power memory sub-system architecture
US7209404B2 · kind B2 · utility
25Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Aug 5, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies, is a major challenge. To reduce leakage, methods and apparatus are presented for memory access and for power- and ground-supply monitoring and management at memory sub-array level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.