Multi-shelf system clock synchronization
US7209530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2003 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Oct 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0691
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for conveying to a control shelf of a multi-shelf network node any master clock signal received via a plurality of interface cards associated with a plurality of peripheral shelves of the multi-shelf network node is presented. The apparatus operating in accordance with the method includes a peripheral shelf controller having: a selector selecting an External SYNChronization (ESYNC) signal from a multitude of ESYNC signals received at an associated peripheral shelf; a comparator deriving phase difference information in comparing the selected ESYNC signal and a SSYNC signal distributed by the control shelf; and encoder for digitally encoding the phase difference information at the peripheral shelf; means for conveying a digital phase difference information digitally between a peripheral shelf and the control shelf. The apparatus further includes a control shelf controller having: a phase difference information stream selector at the control shelf selects a phase difference information stream; an ESYNC regenerator providing to a system synchronization unit an ESYNC signal regenerated from the SSYNC signal and the selected phase difference information stream. Adv…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.