Storage processor architecture for high throughput applications providing efficient user data channel loading
US7209979B2 · kind B2 · utility
4Cited by
9References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 29, 2002 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Jan 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2089
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. The communications architecture provides saturation of user data pathways with low complexity and low latency by employing multiple memory channels under software control, an efficient parity calculation mechanism and other features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.