Methods for optimizing programmable logic device performance by reducing congestion
US7210115B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2004 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Aug 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an optimized implementation. A logic circuit for a programmable logic device can be analyzed by taking into account the effects of hotspots, power supply voltage drops, and signal congestion on device performance. By modeling the performance of transistors and other components using position-dependent and signal-dependent variables such as temperature, voltage, and capacitance, the effects of congestion on device performance can be characterized and an optimum implementation of the logic design in a programmable logic device can be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.