Method of fabricating gate electrode of semiconductor device
US7211491B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2004 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Nov 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a gate electrode of a semiconductor device is disclosed. A disclosed method comprises growing a silicon epitaxial layer on a silicon substrate; making at least one trench through the epitaxial layer and filling the trench with a first oxide layer; etching the first oxide layer to form reverse spacers in the trench; depositing a second oxide layer and a polysilicon layer over the silicon substrate including the trench and the reverse spacers and forming a gate; implanting ions in the silicon substrate at both sides of the gate to form pocket-well and LDD areas; depositing a nitride layer over the silicon substrate including the gate and etching the nitride layer to form spacers; implanting ions using the spacers and the gate as a mask to make a source/drain region; and forming a silicide layer on the top of the gate electrode and the silicon epitaxial layer positioned on the source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.