Semiconductor device and manufacturing method thereof
US7211859B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2005 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Dec 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/221
Abstract
A semiconductor device according to a exemplary embodiment of the present invention includes a reverse spacer exposing a part of an epitaxial silicon layer on a silicon substrate, a gate oxide layer on at least the epitaxial silicon layer and a gate polysilicon layer on the gate oxide layer and at least part of the reverse spacer, and source/drain terminals including a first doped (shallow junction) region in the silicon substrate at a position exterior to the exposed epitaxial silicon layer and a second doped (deep junction) region neighboring the first doped region. The semiconductor device can thus have an epitaxial silicon channel of nanometer size, an ultra-shallow junction, and a deep junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.