Vertical electrical interconnections in a stack

US7211885B2 · kind B2 · utility

Assignee

• Thin Film Electronics ASA · NO

Inventors

• Per-Erik Nordal · Asker, NO
• Hans Gude Gudesen · Fredrikstad, NO
• Geirr Leidstad · Sandvika, NO
• Goran Gustafsson · Säter, SE
• Johan Carlsson · Cologne, DE

Key dates

• Filing date: Mar 14, 2003
• Grant date: May 1, 2007
• Expiry date: Mar 14, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/30105
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwiched self-supporting structure, wherein the layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers the are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.