Capacitive load driving circuit for driving capacitive loads such as pixels in plasma display panel, and plasma display apparatus
US7211963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2005 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | May 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/142
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A capacitive load driving circuit has an input terminal, a front-edge delay circuit delaying a front edge of an input signal input via the input terminal, a back-edge delay circuit delaying a back edge of the input signal, an amplifying circuit amplifying a drive control signal obtained through the front-edge delay circuit and the back-edge delay circuit, and an output switch device which is driven by the amplifying circuit. The front-edge delay circuit includes a first time-constant circuit having a first resistor and a first capacitor, the back-edge delay circuit includes a second time-constant circuit having a second resistor and a second capacitor, and the drive control signal is generated by a signal combining circuit which combines an output signal of the first-time constant circuit with an output signal of the second-time constant circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.