Control signal generation for a low jitter switched-capacitor frequency synthesizer
US7212051B1 · kind B1 · utility
5Cited by
15References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0893
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.