Power supply noise insensitive multiplexer
US7212062B2 · kind B2 · utility
4Cited by
9References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2005 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Jul 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/162
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs while the second places the switches on the analog bias voltages inherent to a current controlled inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.