System for suppressing aliasing interferers in decimating and sub-sampling systems
US7212139B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 15, 2005 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Nov 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0416
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel and useful method and apparatus for suppressing aliasing interferers in decimating and sub-sampling discrete time systems. The present invention is operative to reduce the requirements for or completely eliminate the need for the anti-aliasing filter by dynamically modifying the sub-sampling rate (or decimation ratio). Rather than maintain a constant sampling rate (or decimation ratio), the sampling rate (or decimation ratio) is randomized such that its average remains at the nominal value and the effective jitter is low enough for the low rate (or low decimation ratio) system to tolerate. This smears or spreads interfering signals across the spectrum resulting in a noise floor at a significantly reduced level much lower than that of the original interferer signal. The interfering signals are reduced to background noise wherein the level of the resulting noise floor is not nearly as strong as the original interfering signal. Aliasing interferers are effectively suppressed by spreading the energy of the interfering signals out over a wider spectrum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.