Semiconductor testing device and semiconductor testing method
US7214961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2004 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Nov 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48472
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor testing device of the invention has a measuring substrate that is provided with holes therethrough for exposing a pad of each of the dies of a semiconductor wafer mounted on the measuring substrate, the semiconductor wafer being supported by a wafer holder on one side of the measuring substrate, and the other side of the measuring substrate being provided with a wiring pattern for transmitting an evaluation test signal to the semiconductor wafer supported on the measuring substrate. The measuring substrate, with the pad of each of the dies being wire bonded with a pad of the wiring pattern through the holes, are set for an evaluation test so that a mount part of the semiconductor is placed inside a high temperature chamber, and that a terminal part for applying the evaluation test signal is placed outside of the high temperature chamber. As a result, there is provided a semiconductor testing device, inexpensively, that can suitably evaluate a semiconductor under a temperature of about 400° C., as in EM evaluation for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.