Semiconductor device and semiconductor integrated circuit device
US7214989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2004 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Apr 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
Abstract
Soft-error resistance and latch up resistance are simultaneously improved for LSI involving miniaturization and reducing operating voltage. P wells and N wells are formed in a higher density substrate (P on P+ substrate), and buried N wells are formed on a layer underlying thereof. A PMOSFET is formed in the N well and a NMOSFET is formed in the P well. A P well electric potential junction for coupling P well electric potential of the P well to predetermined electric potential is provided, and a region directly under the P well electric potential junction is provided with a region where the aforementioned buried N well is not disposed. The soft-error resistance is improved by having the buried N well therein, and the latch up resistance is improved by coupling the P well to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.