Semi-clockless, cascaded, current-mode power regulator having high noise immunity and arbitrary phase count
US7215102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2005 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Jul 20, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A semi-clockless, cascaded, current-mode regulator has a first regulator that receives a clock signal from a controller. By ‘semi-clockless’ is meant that a clock signal is applied to the first of a cascaded plurality of regulators, and that as a result of the cascading of clock delay circuits in each of the regulators, the remaining regulators receive sequentially delayed versions of the clock signal applied to the first regulator. The regulators are coupled to control the operations of associated pulse width modulation controlled switching circuits. Outputs of the switching circuits are combined to realize a multi-phase output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.