Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method
US7215140B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2003 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | May 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.