Method for operating a passive matrix-addressable ferroelectric or electret memory device
US7215565B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2005 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Jun 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.