Tracking circuit for a memory device
US7215587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2005 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Dec 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line. The memory device also includes a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.