Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US7215701B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Nov 14, 2002 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Nov 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7083
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding X-component segment of the master scrambling code. For every sixteen (16) chips, a new X-component segment of the master scrambling code is introduced into one of the correlators, a X-component segment of the master scrambling code is dropped from another correlator, and X-component segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators;…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.