Device for WLAN baseband processing with DC offset reduction
US7215722B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 9, 2003 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Apr 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device for processing an intermediate analogue signal received from a previous system with a baseband processor. The processor includes an ordinary feedback loop for adjusting the strength of the intermediate analogue signal received from the previous system. The processor further includes a first DC offset reduction loop and a second DC offset reduction loop. A programmable filter bank and the corresponding control elements are provided so that the second DC offset reduction loop can reduce the DC offset in a flexible way. In the present invention, the DC offset can be reduced effectively and the gain training period relating to the previous system and the baseband processor can be shortened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.