Methods and systems for improving delayed read handling
US7216194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2003 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Oct 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for improving delayed read handling in a loop of delayed commands among a larger set of commands in a queue of commands are disclosed. In general, when commands in a delayed loop are completed out of order, “holes” are left in the command queue. Skipping over such “holes” consumes multiple clock cycles before another command can be issued, as each “hole” must be examined first in order to determine that it no longer contains a valid read command. A loop of delayed read commands can thus be created from among a larger set of commands in a queue of commands with each command entry having a pointer to the next valid command. Valid delayed read commands in the loop of commands can then be processed by automatically advancing between any two valid delayed read commands among the loop of commands. In this manner, the time to advance between any two commands in the delayed read loop is constant and PCI read performance thereof can be dramatically improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.