System and method for providing testing and failure analysis of integrated circuit memory devices
US7216270B1 · kind B1 · utility
5Cited by
3References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2004 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | May 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed for testing integrated circuits that contain memory devices. A plurality of test circuits is created in which each test circuit incorporates a physical fault in a memory bit cell. Each of the test circuits generates a distinct electrical signature that is due to presence of the physical fault in the test circuit. The electrical signatures from the test circuits are compared with a signal from an integrated circuit memory device to determine whether any of the physical faults in the test circuits are present in the integrated circuit memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.