Method of identifying state nodes at the transistor level in a sequential digital circuit using minimum combinatorial feedback loop
US7216307B1 · kind B1 · utility
1Cited by
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29Claims
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Key dates
| Filing date | Jun 27, 2005 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Jul 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.